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Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled xe2x80x9cA True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,xe2x80x9d T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
An attempt to improve the erasure of such ONO EEPROM devices is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of which are hereby incorporated herein by reference. In those disclosed devices, a cell is erased by applying a constant negative voltage to the gate over a plurality of cycles. However, the number of cycles and time to erase the memory cell can become large. Furthermore, the memory cell may become degraded should the number of cycles needed to erase the cell becomes too large. The slowing down of the erase speed is due to the trapping of electrons in the oxide layers or charge spill over into the nitride layer.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. By way of introduction, the preferred embodiments described below relate to a non-volatile read only memory transistor. The transistor includes a channel having a first end comprising a source and a second end comprising a drain. The source being located in a first plane and the drain being located in a second plane with the second plane being oriented substantially parallel to the first plane. Wherein the channel is located in a third plane, the third plane being oriented substantially perpendicular to the first and second planes.
The preferred embodiments further relate to a method for fabricating a non-volatile read only memory device in a substrate. The method comprises: fabricating a trench in the substrate, the trench having a top portion, a bottom portion oriented substantially parallel to the top portion and a wall extending perpendicularly from the top portion to the bottom portion; fabricating a source in the bottom portion of the trench; fabricating a drain in the top portion of the trench; and fabricating a channel in the wall between the source and the drain.